This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-088971, filed Mar. 28, 2000; and No. 2000-302660, filed Oct. 2, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a solid state imaging device having a photodiode and a MOSFET and a method of manufacturing the same.
Many people have recently had an opportunity to capture, process and edit an image with ease as personal computers and personal digital assistants have sprung into wide use. For solid state imaging devices which are constituted chiefly of a CCD, the needs to decrease in size, power consumption and manufacturing costs have grown. To meet these needs, a MOS solid state imaging sensor, which is manufactured based on the general-purpose CMOS semiconductor technique (commonly called a CMOS image sensor), has made an appearance and started to become popular. The CMOS image sensor is currently fabricated with design rules of 0.35 xcexcm or more. In the future, however, it is expected that the CMOS image sensor will be downsized further according to the needs to decrease in size and power consumption.
FIG. 29 is a cross-sectional view showing a prior art MOS solid state imaging device as disclosed in Jpn. Pat. Appln. KOKAI Publication No. 10-150182. In FIG. 29, range A is a pixel region and range B is a peripheral circuit region.
As FIG. 29 shows, polysilicon-made gate electrodes 13a, 13b and 13c are selectively formed on a P-type silicon substrate 11 with a gate insulating film (silicon oxide film) 12 interposed therebetween. In the range A, 13a indicates a readout gate electrode and 13b denotes a reset or address gate electrode. Since a LOCOS (local oxidation of silicon) structure (hereinafter referred to as LOCOS) is generally used in a non-fine pattern formed with design rules of 0.35 xcexcm or more, an element isolation region of the LOCOS structure is selectively formed in the silicon substrate 11.
In the range A, an N-type drain region 14a and an N-type signal storage region 15 for a photodiode are formed in a desired area of the surface of the silicon substrate 11. A P+-type surface shield region 21 is formed on the surface of the region 15. Thus, P+NP-type buried photodiodes 34a and 34b for storing signal charges corresponding to an amount of incident light are formed. In the range B, an N-well and a P-well are formed in the silicon substrate 11, and a P-type source and drain region 14b and an N-type source and drain region 14c are formed in the N-well and the P-well, respectively.
A first interlayer insulating film 25 is formed on the entire surface of the resultant structure, and a second interlayer insulating film 27 is formed on the film 25. An Al light-shielding film 28 is formed on the film 27. The film 28 has an opening 30 through which light is incident upon the photodiodes 34a and 34b. An Al wiring layer 26 is selectively formed in the second interlayer insulating film 27 and on the first interlayer insulating film 25. The layer 26 serves as a signal line and a connection line in units of pixels. A surface protection film 29 such as a silicon nitride film is formed on the top of the structure. In some cases, intermediate refracting films such as Ti and TiN films can be provided on the tops and undersides of the Al wiring layer 26 and the Al light-shielding film 28 to prevent light from being reflected therefrom (as disclosed in Jpn. Pat. Appln. KOKAI Publication No. 11-45989).
In the MOS solid state imaging device so constituted, the signal charges stored in the signal storage region 15 are read out of the N-type drain region 14a if a positive voltage is applied to the readout gate electrode 13a, thus modulating the potential of the drain region 14a. The region 14a is electrically connected to the gate electrode 13b of an amplification transistor, and an electrical signal amplified by the gate electrode 13b is output from the Al wiring layer 26 of the signal line.
However, stray light produces a greatly adverse effect as one problem caused when the pixels are downsized further in the prior art solid state imaging device described above.
The stray light means part of light incident upon the photodiodes 34a and 34b which is reflected by the surface of the silicon substrate 11 and then multi-reflected by the surfaces of the Al wiring layer 26, drain region 14a and gate electrode 13b and which goes in the distance. In the device shown in FIG. 29, the surfaces of the gate electrodes 13a to 13c and those of the source and drain regions 14a to 14c are made of silicon materials whose reflectivity is as high as 40% or more in a visible-light region. For this reason, stray light reflected by the surface of the photodiode 34a does not attenuate sufficiently but reaches its adjacent photodiode 34b, thereby causing a false signal such as smear and blooming.
If an interval between the photodiodes 34a and 34b shorten as the pixels decrease in size, it is natural that more intensive stray light enters a nearer photodiode, with the result that a false signal such as smear and blooming is easy to occur. Since the stray light does not attenuate sufficiently, it arrives at the source and drain regions 14b and 14c and the gate electrode 13c in the peripheral circuit region (range B) to cause the transistor to malfunction. In future, therefore, an adverse effect of the stray light will be increased more greatly as the pixels are downsized.
Currently the CMOS image sensor employs a power supply voltage of 3.3V or higher. It is expected that a CMOS image sensor operating at a power supply voltage of 3.3V or lower will be developed according to the above micromachining of 0.35 xcexcm or less in order to decrease the size and power consumption of the solid state imaging device further.
However, using a buried photodiode structure in which a surface shield region of a conductivity type other than that of the signal storage region is formed on the surface of the photodiode, the problem of a decrease in power supply voltage of the readout gate electrode will become more serious.
FIG. 30A is a cross-sectional view of the buried photodiode which is part of the range A in FIG. 29. FIGS. 30B and 30C show potentials in low-voltage read mode (when the read gate electrode turns on). In FIG. 30C, charges are read out at a voltage lower than that in FIG. 30B.
As FIG. 30A illustrates, an element isolation region of the LOCOS structure is selectively formed in the P-type silicon substrate 11, and the readout gate electrode 13a is selectively formed on the silicon substrate 11 with the gate insulating film 12, such as a silicon oxide film, interposed therebetween. The N-type drain region 14a, N-type signal storage region 15 and P+-type surface shield region 21 are formed on the surface of the silicon substrate 11 by ion implantation. Thus, the photodiode 34a is obtained. Both the silicon substrate 11 and the surface shield region 21 are grounded at a reference potential.
In the solid state imaging device described above, when light is incident upon the photodiode 34a, the incident light is photoelectrically converted into a signal electron, and the signal electron is stored in the signal storage region 15. The surface shield region 21 serves to both prevent an interface of the gate insulating film 12 between Si and SiO2 from being depleted to reduce junction leakage currents and to set potential 42 of the signal storage region 15 between the surface shield region 21 and silicon substrate 11 lower than channel potential 43 under the gate electrode 13a which is modulated by turning on the readout gate electrode 13a. In principle, the signal electrons can completely be transferred from the signal storage region 15 to the drain region 14a. 
In the prior art solid state imaging device shown in FIG. 30A, however, the surface shield region 21 is all buried into the silicon substrate 11. Thus, the top surface of the region 21 is located lower than the underside of the readout gate electrode 13a. As illustrated in FIG. 30B, therefore, a potential barrier 41 occurs in a potential barrier occurring section 40 at one end of the surface shield region 21. As a result, charges 44 are not transferred completely but remain in the signal storage region 15, which causes not a little image lags and not a little noise.
When a power supply voltage drops by request or when a voltage (readout voltage) drops in the ON state of the readout gate electrode 13a (e.g., the readout voltage drops to about 2.5V from the conventional value of 3.3V), the potential barrier 41 becomes higher and more charges 45 remain as shown in FIG. 30C. Consequently, the image lags and noise increase more greatly and the sensitivity of the device lowers greatly, which are serious problems in practical use.
As described above, recently, an adverse effect of stray light has been increased more greatly as the elements have been downsized and a false signal including smear and blooming has occurred easily. Moreover, a potential barrier becomes greater as a power supply voltage lowers and accordingly image lags and noise increase further. The prior art solid state imaging device therefore causes the problem of decreasing elements due to various types of noise caused by request of element downsizing and lower power supply voltage and thus decreasing the performance of the elements.
The present invention has been developed in order to resolve the above problems and its object is to provide a solid state imaging device capable of improving the performance of elements and a method of manufacturing the same.
To attain the above object, a solid state imaging device according to a first aspect of the present invention comprises a gate insulating film formed on a semiconductor substrate of a first conductivity type, a readout gate electrode selectively formed on the gate insulating film, a diffusion region of a second conductivity type formed on a surface of the semiconductor substrate at one end of the readout gate electrode, a signal storage region of the second conductivity type formed on the surface of the semiconductor substrate at other end of the readout gate electrode, a surface shield region of the first conductivity type formed on a surface of the signal storage region, a silicide block layer covering at least part of the signal storage region, and a metal silicide layer formed on the diffusion region.
A solid state imaging device according to a second aspect of the present invention comprises a gate insulating film formed on a semiconductor substrate of a first conductivity type, a readout gate electrode selectively formed on the gate insulating film, a diffusion region of a second conductivity type formed on a surface of the semiconductor substrate at one end of the readout gate electrode, a signal storage region of the second conductivity type formed on the surface of the semiconductor substrate at other end of the readout gate electrode, and a surface shield region of the first conductivity type formed on the signal storage region higher than the surface of the semiconductor substrate.
A solid state imaging device according to a third aspect of the present invention comprises a silicide block layer covering at least part of the signal storage region and a metal silicide layer formed on the diffusion region in addition to the constituting elements of the solid state imaging device according to the second aspect.
In the solid state imaging devices according to the first and second aspects, the semiconductor substrate can be formed of one of a well layer and an epitaxial growth layer.
In the solid state imaging devices according to the second and third aspects, the diffusion region can be formed higher than the surface of the semiconductor substrate.
In the solid state imaging devices according to the first and third aspects, the metal silicide layer can be formed of one of a Ti silicide film, a Co silicide film, a Ni silicide film, and a W silicide film.
In the solid state imaging devices according to the first and third aspects, it is preferable that the silicide block layer should cover at least part of the signal storage region and at least part of the readout gate electrode. The silicide block layer may cover at least part of the signal storage region, at least part of the readout gate electrode, and at least part of the diffusion region.
In the solid state imaging devices according to the second and third aspects, it is preferable that the surface shield region should have an underside which is flush with that of the readout gate electrode.
The solid state imaging devices according to the third aspect may further comprises a gate electrode separated from the readout gate electrode at a predetermined interval, source and drain regions formed at both ends of the gate electrode higher than the surface of the semiconductor substrate, and a metal silicide layer formed on the source and drain regions.
A solid state imaging device according to the present invention may comprise a readout gate electrode selectively formed on a semiconductor substrate of a first conductivity type with a gate insulating film interposed therebetween, a diffusion region of a second conductivity type formed on a surface of the semiconductor substrate at one end of the readout gate electrode, a metal silicide layer formed on a surface of the diffusion region, a signal storage region of the second conductivity type formed on the surface of the semiconductor substrate at other end of the readout gate electrode, a surface shield region of the first conductivity type formed on a surface of the signal storage region, a sidewall insulating film formed on a side of the one end of the readout gate electrode, and a silicide block layer covering a side of the other end of the readout gate electrode, at least part of a surface of the readout gate electrode, and at least part of the signal storage region.
A method of manufacturing a solid state imaging device according to a first aspect of the present invention, comprises the steps of forming a first insulating film on a semiconductor substrate of a first conductivity type, selectively forming an element isolation region for separating an element region in the semiconductor substrate, forming a readout gate electrode on the element region with the first insulating film interposed therebetween and a gate electrode on the element isolation region with the first insulating film interposed therebetween, forming a diffusion region of a second conductivity type on a surface of the element region at one end of the readout gate electrode, forming a signal storage region of the second conductivity type on the surface of the element region at other end of the readout gate electrode, forming a second insulating film on an entire surface of a resultant structure, removing the second insulating film and forming a silicide block layer covering at least part of the signal storage region, forming a surface shield region of the first conductivity type on a surface of the signal storage region, removing the first insulating film and the second insulating film from the diffusion region to expose a surface of the diffusion region, and forming a metal silicide layer on the exposed surface of the diffusion region.
A method of manufacturing a solid state imaging device according to a second aspect of the present invention, comprises the steps of forming a first insulating film on a semiconductor substrate of a first conductivity type, selectively forming an element isolation region for separating an element region in the semiconductor substrate, forming a readout gate electrode on the element region with the first insulating film interposed therebetween, forming a diffusion region of a second conductivity type on a surface of the element region at one end of the readout gate electrode, forming a signal storage region of the second conductivity type on the surface of the element region at other end of the readout gate electrode, and forming a surface shield region of the first conductivity type by selectively epitaxial-growing a silicon layer of the signal storage region.
A method of manufacturing a solid state imaging device according to a third aspect of the present invention, comprises the steps of forming a first insulating film on a semiconductor substrate of a first conductivity type, selectively forming an element isolation region for separating an element region in the semiconductor substrate, forming a readout gate electrode on the element region with the first insulating film interposed therebetween, forming a diffusion region of a second conductivity type on a surface of the element region at one end of the readout gate electrode, forming a signal storage region of the second conductivity type on the surface of the element region at other end of the readout gate electrode, forming a selective growth silicon layer by selectively epitaxial-growing a silicon layer of the signal storage region and the diffusion region, forming a surface shield region of the first conductivity type in the selective growth silicon layer on the signal storage region, forming a second insulating film on an entire surface of a resultant structure, removing the second insulating film so as to expose at least a surface of the selective growth silicon layer on the diffusion region and forming a silicide block layer covering at least part of the signal storage region, and forming a metal silicide layer on the exposed surface of the selective growth silicon layer on the diffusion region.
In the methods according to the second and third aspects of the present invention, the surface shield region can be formed by selectively growing a silicon layer into which no ions are implanted and then subjecting the selectively grown silicon layer to ion implantation and heat treatment. The surface shield region can also be formed by selectively growing a silicon layer into which ions are implanted.
The methods according to the first and third aspects of the present invention may further comprise a step of removing the silicide block layer after the metal silicide layer is formed.
In the solid state imaging devices and the methods described above, the elements can be improved in performance.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.